Job Description

Senior Design Verification Engineer

Experience Level: 5-20 years of experience

JOB DESCRIPTION 1: Sunnyvale CA

General DV skills, someone who can understand the specs, work with designers, write SV tests, and good at debug. Experience in writing testcase using c/c++ for ARM cores. Debugging test failures in C and SV-UVM mixed environment.

JOB DESCRIPTION 2: Sunnyvale CA

DV background, but more focused or specialized in the python scripting, tool implementation using python, looking for mid/sr level experience.

JOB DESCRIPTION 3: Sunnyvale CA

Proficiency in modern Python (intermediate or above)

Understanding of basic data structures and algorithms

Hands-on experience in SystemVerilog/UVM

Knowledge of UVM RAL (Register Abstraction Layer)

Experience in development in Linux based environments (Bash scripting, Makefile)

Plus:

Experience in development of UVM based verification environments

Experience in EDA tools and scripting used to build tools and flows for verification environments

Experience with revision control systems like Git or Mercurial(Hg)

JOB DESCRIPTION 4: Austin TX, San Jose CA

1. Very fast paced environment.
2. Excellent SV/UVM knowledge.
3. Good to have: LPDDR/DDR protocol knowledge.

JOB DESCRIPTION 5: San Jose CA

1. Excellent SV/UVM knowledge.
2. Must have experience in PCie Gen 4/5/6

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